# a variable named CC refers to the name of the compiler to use
CC = gcc

# rules
# target: prerequisites
#	command 1
#	command 2
# 	...

# the first target is always the default target
# if "make" is run without explicit target, these commands are executed
all: hello # "all" target depends on "hello" target 

# compilation
hello.o: hello.c
	$(CC) -c hello.c -o hello.o

# linking
hello: hello.o
	$(CC) hello.o -o hello

clean:
	rm -f hello hello.o